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single-chip, multiband 3g femtocell transceiver adf4602 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009C2011 analog devices, inc. all rights reserved. features single-chip, multiband 3g transceiver 3gpp 25.104 release 9 wcdma/hspa compatible umts band coverage local area class bs in band i to band vi and band viii to band x direct conversion transmitter and receiver minimal external components integrated, multiband, multimode monitoring no tx saw or rx interstage saw filters integrated power management (3.1 v to 3.6 v supply) integrated synthesizers, including pll loop filters integrated pa bias control dacs/gpos wcdma and gsm receive baseband filter options easy-to-use with minimal calibration automatic rx dc offset control simple gain, frequency, mode programming low supply current 50 ma typical rx current 50 ma to 100 ma tx current (varies with output power) 6 mm 6 mm 40-pin lfcsp package applications 3g home base stations (femtocells) functional block diagram dac1 dac2 gpo 1 to 4 tx_pwr_control tx_pwr_ control txbbib txbbi txbbq txbbqb vsup7 vsup6 rxbbi rxbbib vdd rxlbrf rxhb2rf rxhb1rf txlbrf rxbbq rxbbqb dac1 dac2 gpo[4:1] tx_pwr_control tx_pwr_ control txhbrf loop filter rx pll rx_lo_lb selectable bandwidth baseband filters rx_lo_lb frac n synthe- sizer lo generator loop filter frac n synthe- sizer lo generator dc offset correction serial inter- face dc offset correction q chan- nel i chan- nel vsup8 26mhz 19.2mhz adf4602 vint refclk c hipcl k vsup2 ldo2 vsup3 ldo3 vsup4 ldo4 vsup5 ldo5 tx pll 07092-001 vsup1 ldo1 refin sen sclk sdata figure 1.
adf4602 rev. a | page 2 of 36 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? general description ......................................................................... 3 ? specifications..................................................................................... 4 ? timing characteristics..................................................................... 8 ? absolute maximum ratings............................................................ 9 ? esd caution.................................................................................. 9 ? pin configuration and function descriptions........................... 10 ? typical performance characteristics ........................................... 12 ? theory of operation ...................................................................... 19 ? transmitter description ............................................................ 19 ? dacs ............................................................................................ 20 ? general purpose outputs.......................................................... 20 ? receiver description.................................................................. 20 ? power management ................................................................... 23 ? frequency synthesis................................................................... 24 ? serial port interface (spi).............................................................. 25 ? operation and timing............................................................... 25 ? registers........................................................................................... 26 ? register map ............................................................................... 26 ? register description .................................................................. 27 ? software initialization procedure................................................. 31 ? initialization sequence .............................................................. 31 ? applications information .............................................................. 33 ? interfacing the adf4602 to the ad9963................................ 33 ? outline dimensions ....................................................................... 35 ? ordering guide .......................................................................... 35 ? revision history 2/11rev. 0 to rev. a changes to features and applications........................................... 1 changes to table 1............................................................................ 4 changes to table 3............................................................................ 9 changes to figure 4........................................................................ 10 changes to figure 13...................................................................... 13 changes to figure 21 and figure 22............................................. 14 changes to figure 26 and figure 27............................................. 15 changes to figure 31 through figure 33 ..................................... 16 changes to figure 44...................................................................... 21 changes to dc offset compensation section ........................... 23 changes to figure 51...................................................................... 26 changes to table 13........................................................................ 30 replaced applications information section ............................... 33 changes to figure 53...................................................................... 34 10/09revision 0: initial version
adf4602 rev. a | page 3 of 36 general description the adf4602 is a 3g transceiver integrated circuit (ic) offering unparalleled integration and feature set. the ic is ideally suited to high performance 3g femtocells providing cellular fixed mobile converged (fmc) services. with only a handful of external components, a full multiband transceiver is implemented. umts band i through band vi and band viii through band x are supported in a single device. the receiver is based on a direct conversion architecture. this architecture is the ideal choice for highly integrated wideband cdma (wcdma) receivers, reducing the bill of materials by fully integrating all interstage filtering. the front end includes three high performance, single-ended low noise amplifiers (lnas), allowing the device to support tri-band applications. the single-ended input structure eases interface and reduces the matching components required for small footprint single- ended duplexers. the excellent device linearity achieves good performance with a large range of saw and ceramic filter duplexers. the integrated receive baseband filters offer selectable bandwidth, enabling the device to receive both wcdma and gsm-edge radio signals. the selectable bandwidth filter, coupled with the multiband lna input structure, allows gsm-edge signals to be monitored as part of a umts home base station. the transmitter uses an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise, eliminating the need for external transmit saw filters. the fully integrated phase lock loops (plls) provide high performance and low power fractional-n frequency synthesis for both receive and transmit sections. special precautions have been taken to provide the isolation demanded by frequency division duplex (fdd) systems. all vco and loop filter components are fully integrated. the adf4602 also contains on-chip low dropout voltage regulators (ldos) to deliver regulated supply voltages to the functions on chip, with an input voltage of between 3.1 v and 3.6 v. the ic is controlled via a standard 3-wire serial interface with advanced internal features allowing simple software programming. comprehensive power-down modes are included to minimize power consumption in normal use.
adf4602 rev. a | page 4 of 36 specifications v dd = 3.1 v to 3.6 v, gnd = 0 v, t a = t min to t max , unless otherwise noted. typical specifications are at v dd = 3.3 v and t a = 25c, 26 mhz reference input level = 0.7 v p-p. table 1. parameter min typ max unit test conditions reference section reference input reference input frequency 26 mhz reference input amplitude 0.1 0.7 2.0 v p-p single-ended operation, dc-coupled 1 reference input jitter 1.5 ps rms refclk output (26 mhz) output load capacitance 10 40 pf output swing 1.5 v p-p 10 pf load output slew rate 200 v/s 10 pf load output duty cycle variation 2 % input duty cycle = 50% output jitter 1.5 ps rms chipclk output (19.2 mhz) output load capacitance 10 40 pf frequency multiplication ratio 48/65 48/65 n/a output swing 1.5 v p-p 10 pf load output duty cycle variation 2 % input duty cycle = 50% output jitter 33 ps rms lock time 50 s transmit section i/q input input resistance 100 k single-ended input capacitance 2 pf single-ended differential peak input voltage 500 550 mv pd input common-mode voltage 1.05 1.2 1.4 v baseband filter 3 db bandwidth 4.0 mhz tx gain control maximum gain 5 db 1 v p-p differential baseband input gain control range 60 db gain control resolution 1/32 db average of lsb steps gain control accuracy 1.0 db any 1 db step 10 db any 10 db step gain settling time 1 s p out within 0.1 db of final value rf specifications (high band) carrier frequency 1710 2170 mhz output impedance 50 output power (p out ) ?8 dbm tm1 signal 64 dpch output noise spectral density ?155 dbc/hz 40 mhz offset ?161 dbc/hz 80 mhz offset ?161 dbc/hz 95 mhz offset ?163 dbc/hz 190 mhz offset carrier leakage ?35 dbc p out = ?8 dbm fdd evm 5 % p out = ?8 dbm fdd aclr 55 db 5 mhz, p out = ?8 dbm 70 db 10 mhz, p out = ?8 dbm
adf4602 rev. a | page 5 of 36 parameter min typ max unit test conditions rf specifications (low band) carrier frequency 824 960 mhz output impedance 50 output power (p out ) ?6 dbm tm1 signal 64 dpch output noise spectral density ?158 dbc/hz 45 mhz offset carrier leakage ?35 dbc p out = ?6 dbm fdd evm 5 % p out = ?6 dbm fdd aclr 55 db 5 mhz, p out = ?6 dbm 70 db 10 mhz, p out = ?6 dbm receive section baseband i/q output output common mode voltage 1.15 1.2 1.35 v mode 1 1.35 1.4 1.55 v mode 2 differential output range 4 v p-p d output dc offset 5 mv quadrature gain error 0.3 0.7 db quadrature phase error 1 rms in-band gain ripple 0.2 db low-pass filter rejection (check) wcdma (seventh order) 20 db @2.7 mhz 42 db @3.5 mhz 80 db @5.9 mhz 110 db @10 mhz wcdma (fifth order) 14 db @2.7 mhz 31 db @3.5 mhz 55 db @5.9 mhz 80 db @10 mhz gsm 12 db @200 khz 47 db @400 khz 90 db @800 khz differential group delay wcdma 250 ns 1.92 mhz band gsm 200 ns 100 khz band receiver gain control maximum voltage gain 102 db wcdma mode gain control range 90 db gain control resolution 1 db gain control step error 1 db 1 db step 2 db 10 db step rf specifications (high band) input frequency 1710 2170 mhz input impedance 50 input return loss ?20 db noise figure 4.0 db tx power of ?8 dbm, spur-free measurement 2 maximum input power 3 ?20 dbm maximum lna gain ?2 dbm minimum lna gain input ip3 ?7 dbm 10 mhz and 20 mhz offset, 59 db gain 0 85 mhz and 190 mhz offset, 59 db gain input ip2 53 dbm 80 mhz offset 65 dbm 190 mhz offset evm 8 % ?60 dbm input rf specifications (low band)
adf4602 rev. a | page 6 of 36 parameter min typ max unit test conditions input frequency 824 960 mhz input impedance 50 input return loss ?20 db noise figure 4.0 db 80 db gain, tx power of ?8 dbm maximum input power 3 ?20 dbm maximum lna gain ?2 dbm minimum lna gain input ip3 2 dbm 10 mhz and 20 mhz offset, 59 db gain 5 dbm 45 mhz and 90 mhz offset, 59 db gain input ip2 40 dbm 45 mhz offset evm 7 % ?60 dbm input synthesizer section channel resolution 50 khz lock time 3 200 s dac/gpo control dac1 resolution 5 bits output range 2.3 3.15 v v dd > 3.15 v absolute accuracy 50 mv any code, v dd > 3.2 v output lsb step 25 mv output capacitive load 1 nf output current ?10 +10 ma output impedance 1 dac2 resolution 6 bits output range 0 2.85 v dnl 0.5 lsb no load inl 1.0 lsb no load output capacitive load 1 nf output current ?5 +5 ma output impedance 5 gpo1 to gpo4 output current 2 ma gpo1, gpo2, gpo3 10 ma gpo4 output high voltage 2.6 v maximum output current output low voltage 0.2 v maximum output current switching time 1 s 5 pf load logic inputs input high voltage, v inh 1.2 2.1 v 1.8 v readback mode 4 input high voltage, v inh 1.2 3.3 v 2.8 v readback mode 4 input low voltage, v inl 0.6 v input current, i inh /i inl 1 a input capacitance, c in 10 pf logic outputs (sdata) output high voltage, v oh v x ? 0.45 v v x = vint or vsup8, i oh = 500 a output low voltage, v ol 0.45 v i ol = 500 a clk out rise/fall 5 ns clk out load 10 pf temperature range (t a ) 0 85 c
adf4602 rev. a | page 7 of 36 parameter min typ max unit test conditions power supplies voltage supply vdd 3.1 3.3 3.6 v main supply input vsup1 2.6 v output from internal ldo1, 10 ma rating, supply for rx vco vsup2 2.8 v output from internal ldo2, 30 ma rating, supply for rx baseband and rx down- converter vsup3 1.9 v output from internal ldo3, 10 ma rating, supply for rx lnas vsup4 2.6 v output from internal ldo4, 10 ma rating, supply for tx vco vsup5 2.8 v output from internal ldo5, 100 ma rating, supply for tx modulator, tx baseband, pa control dacs vsup6 1.9 v supply input for rx synthesizer, connect to vsup3 vsup7 1.9 v supply input for tx synthesizer, connect to vsup3 vsup8 2.8 v supply input for reference section, connect to vsup2 vint 1.6 1.8 2.0 v supply input for serial interface control logic current consumption transmit current consumption v dd = 3.6 v, output is matched into 50 ?8 dbm output level 100 ma f rf = 2170 mhz ?28 dbm output level 50 ma f rf = 2170 mhz receive current consumption 50 ma 1 the reference frequency should be dc coupled to the refin pin. it is ac-coupled internally. 2 the noise figure measurement does not include spurious noise due to harmonics of the 26 mhz reference frequency. spurs appear at integer multiples of the reference frequency (every 26 mhz), degrading the receive sensitivity by about 6 db. 3 guaranteed by design, not production tested. 4 bit sif_vsup8 in register 2 controls whether 1.8 v readback mode or 2.8 v readback mode is selected. see the s section for more details. erial port inter face (spi)
adf4602 rev. a | page 8 of 36 timing characteristics v dd = 3.1 v to 3.6 v, vgnd = 0 v, t a = 25c, unless otherwise noted. guaranteed by design but not production tested. table 2. parameter limit at t min to t max unit test conditions/comments t 1 62 ns min sen high to write time t 2 10 ns min sen to sclk setup time t 3 10 ns min sdata to sclk setup time t 4 10 ns min sdata to sclk hold time t 5 31 ns min sclk high duration t 6 31 ns min sclk low duration t 7 10 ns min sen to sclk hold time t 8 20 ns max sen to sdata valid delay t 9 20 ns max sclk to sdata valid delay t 10 20 ns max sen to sdata disabled delay w[25] w[24] w[1] sclk sdata sen w[0] write t 3 t 2 t 7 t 1 t 4 t 6 t 5 07092-002 figure 2. serial interface write diagram q[25] q[24] q[1] sclk sdata sen q[0] r[25] r[24] r[1] r[0] 3ormore sysclk periods dbb releases rsdata selected device drives rsdata read read request 07092-003 t 8 t 10 t 9 3 or more sclk periods host releases sdata adf4602 drives sdata figure 3. serial interface read/write diagram
adf4602 rev. a | page 9 of 36 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating vdd to gnd ?0.3 v to +4 v vsup1, vsup2 to gnd ?0.3 v to +3.6 v vsup4, vsup5, vsup6, vsup7, vsup8, vsup9 to gnd ?0.3 v to +3.6 v vsup3 to gnd ?0.3 v to +2.0 v vint to gnd ?0.3 v to +2.0 v analog i/o voltage to gnd ?0.3 v to vdd + 0.3 v digital i/o voltage to gnd ?0.3 v to vdd + 0.3 v operating temperature range commercial (b version) 0c to +85c storage temperature range ?65c to +125c maximum junction temperature 150c lfcsp ja thermal impedance 32c/w reflow soldering based on j-std-020 peak temperature 260c number of reflows 3 time at peak temperature 40 sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf integrated circuit with an esd rating of <2 kv, and it is esd sensitive. proper precautions should be taken for handling and assembly. esd caution
adf4602 rev. a | page 10 of 36 pin configuration and fu nction descriptions notes 1. nc = no conne c t. do not connect to this pin. 2. the exposed paddle must be connected to ground for correct chip operation. it provides both a therm a l and electrical connection to the pcb. 07092-004 1 gpo3 2 vsup1 3 vsup3 4 rxlbrf 5 nc 6 rxhb2rf 7 rxhb1rf 8 rxbbi 9 rxbbib 10 rxbbq 23 txbbqb 24 txlbrf 25 txrfgnd 26 txhbrf 27 txrfgnd 28 vsup5 29 dac2 30 dac1 22 txbbq 21 vsup4 1 1 r x b b q b 1 2 v s u p 2 1 3 v i n t 1 5 s c l k 1 7 n c 1 6 s e n 1 8 v s u p 7 1 9 t x b b i 2 0 t x b b i b 1 4 s d a t a 3 3 c h i p c l k 3 4 v s u p 8 3 5 r e f c l k 3 6 r e f i n 3 7 n c 3 8 v s u p 6 3 9 g p o 1 4 0 g p o 2 3 2 g p o 4 3 1 v d d adf4602 top view (not to scale) pin 1 indicator figure 4. pin configuration table 4. pin function descriptions pin no. mnemonic function 1 gpo3 general purpose output 3. digital output. th is is used for external switch or pa control. 2 vsup1 1 output from ldo 1. supply for receive vco. nominal valu e of 2.6 v. 100 nf decoupling to ground is required. 3 vsup3 1 output from ldo 3. supply for receive lna. nominal valu e of 1.9 v. 100 nf decoupling to ground is required. 4 rxlbrf receive low band lna input. 5 nc no connect. do not connect to this pin. 6 rxhb2rf receive second high band lna input. use for umts band ii. 7 rxhb1rf receive first high band lna input. use for umts band i. 8 rxbbi receive baseband i output. 9 rxbbib complementary receive baseband i output. 10 rxbbq receive baseband q output. 11 rxbbqb complementary receive baseband q output. 12 vsup2 1 output from ldo 2. supply for receive downconverter and baseband. nominal value of 2.8 v. 100 nf decoupling to ground is required. 13 vint serial port supply input. 1.8 v should be applied to this pin. 14 sdata serial port data pin. th is can be an input or output. 15 sclk serial clock input. 16 sen serial port enable input. 17 nc no connect. do not connect to this pin. 18 vsup7 1 transmit synthesizer supply input. connect to vsup3 and decouple with 100 nf to ground. 19 txbbi transmit baseband i input. 20 txbbib complementary tx baseband i input. 21 vsup4 1 output from ldo4. supply for transmit vco. nominal va lue of 2.8 v. 100 nf decoupling to gnd is required. 22 txbbq transmit baseband q input. 23 txbbqb complementary tx baseband q input. 24 txlbrf low band transmit rf output. this can output in the range of 824 mhz to 960 mhz. 25 txrfgnd transmit rf ground. connect this pin to ground. 26 txhbrf high band transmit rf output. this can output in the range of 1710 mhz to 2170 mhz. 27 txrfgnd transmit rf ground. connect this pin to ground. 28 vsup5 1 output from ldo 5. supply for transmit modulator, baseband, power detector, and dacs. nominal value of 2.8 v. 100 nf decoupling to ground is required. 29 dac2 output from dac2. 30 dac1 output from dac1.
adf4602 rev. a | page 11 of 36 pin no. mnemonic function 31 vdd main supply input. 32 gpo4 digital output. this is used for switch or pa control. 33 chipclk chip clock output. 34 vsup8 1 reference clock supply input. connect to vsup2, and decouple to ground with 100 nf. 35 refclk reference clock output. 36 refin reference clock input. the reference is ac-coupled internally. 37 nc no connect. do not connect to this pin. 38 vsup6 1 receive synthesizer supply input. connect to vsup3 and decouple to ground with 100 nf. 39 gpo1 digital output. this is used for switch or pa control. 40 gpo2 digital output. this is used for switch or pa control. epad exposed paddle under chip. this must be connected to ground for correct chip operation. it provides both a thermal and electrical connection to the pcb. 1 y5v capacitors are not recommend ed for use with these pins. x7r, x5r, c0g or a similar type of capacitor should be used.
adf4602 rev. a | page 12 of 36 typical performance characteristics a b 3db ref 3.90 dbm ref 3.90 dbm ref 3.90 dbm att* 0db att* 0db code power relative cf 2.1399994 g h cpich slot 0 chan code 0 3db 1 view chan slot 0 ref 3.90 dbm ref 3.90 dbm ref 3.90 dbm 1 clrwr result summar y cf 2.1399994 g h cpich slot 0 chan code 5 chan slot 0 att* 0db att* 0db start ch 0 64 ch / sto p ch 511 sr 240 ks p s sr 240 ks p s -63 - 5 6 -49 -42 - 3 5 - 2 8 -21 -14 - 7 global results for frame 0: total power chip rate error iq offset composite evm cpich slot no -8.03 0.95 1.83 2.54 0 dbm ppm % % carrier freq error trigger to frame iq imbalance pk cde (15 ksps) no of active chan 65.98 9.642977 0.23 -50.12 44 hz ms % db channel results symbol rate channel code no of pilot bits channel power rel symbol evm 240.00 5 0 -0.04 2.43 ksps db %rms timing offset channel slot no modulation type channel power abs symbol evm rho 0 0 16qam -19.05 7.02 0.99936 chips dbm %pk global results for frame 0: total power chip rate error iq offset composite evm cpich slot no -8.03 0.95 1.83 2.54 0 dbm ppm % % carrier freq error trigger to frame iq imbalance pk cde (15 ksps) no of active chan 65.98 9.642977 0.23 -50.12 44 hz ms % db channel results symbol rate channel code no of pilot bits channel power rel symbol evm 240.00 5 0 -0.04 2.43 ksps db %rms timing offset channel slot no modulation type channel power abs symbol evm rho 0 0 16qam -19.05 7.02 0.99936 chips dbm %pk global results for frame 0: total power chip rate error iq offset composite evm cpich slot no -8.03 0.95 1.83 2.54 0 dbm ppm % % carrier freq error trigger to frame iq imbalance pk cde (15 ksps) no of active chan 65.98 9.642977 0.23 -50.12 44 hz ms % db channel results symbol rate channel code no of pilot bits channel power rel symbol evm 240.00 5 0 -0.04 2.43 ksps db %rms timing offset channel slot no modulation type channel power abs symbol evm rho 0 0 16qam -19.05 7.02 0.99936 chips dbm %pk 07092-006 figure 5. umts band i transmit evm, test model 5, 2.5% evm cpich slot 0 sr 15 ks p s chan code 0 chan slot 0 b ln ln cf 881.5 mhz result summar y db cf 881.5 mhz code pwr relative code pwr relative cpich slot 0 cpich slot 0 sr 15 ksps chan code 0 chan code 0 chan slot 0 chan slot 0 2 2 a ln ref lvl r e f l v l 6 dbm ref lvl r e f l v l 6 dbm start: ch 0 stop: ch 511 64 ch/div ref lvl r e f l v l 6 dbm ref lvl r e f l v l 6 dbm -63 -56 -49 -42 -35 -28 -21 -7 -70 0 result summary global results 3 total pwr -4.57 dbm 3 carr freq err -92.42 hz chip rate err 1.04 ppm 3 trg to frame 22.62 ? s iq offset 0.79 % 3 iq imbalance 0.36 % composite evm 2.04 % rms 3 pk code dom err -49.96 db rms cpich slot number 0 3 ( 15 ksps) channel results 3 symb rate 15 ksps 3 timing offset 0 chips channel code 0 3 chan slot number 0 modulation type qpsk 3 no. of pilot bits 0 chan pow rel. 0.00 db 3 chan pow abs. -14.60 dbm symbol evm 0.74 % rms 3 symbol evm 1.21 % pk 07092-005 figure 6. umts band v transmit evm, test model 1, 64 dpch, 2% evm 20 18 16 14 12 10 8 6 4 2 0 35 30 25 20 15 10 5 0 5 txpwr_set (dbm) composite evm (%) 07092-007 dut 1 dut 4 dut 6 dut 8 dut 10 dut 2 dut 5 dut 7 dut 9 dut 3 30db dynamic range <6% evm figure 7. txhbrf, umts band i. transm it evm vs. txpwr_set (dbm), measured across 10 duts, four calibration points applied, transmit frequency 2140 mhz 0 2 4 6 8 10 12 14 16 18 20 35 30 25 20 15 10 5 0 5 composite evm (%) txpwr_set (dbm) 07092-107 figure 8. txhbrf, umts band ii. transmit evm vs. txpwr_set (dbm), four calibration poin ts applied, transmit frequency 1960 mhz. 0 2 4 6 8 10 12 14 16 18 20 35 30 25 20 15 10 5 0 5 composite evm (%) txpwr_set (dbm) 07092-108 figure 9. txlbrf,umts band v, tr ansmit evm vs. tpwr_set (dbm), four calibration poin ts applied, transmit frequency 881 mhz. 30 35 40 45 50 55 60 65 70 14 12 10 8 6 4 output power (dbm/3.84mhz) aclr (db) 07092-008 +5mhz ?5mhz +10mhz ?10mhz figure 10. txhbrf transmit aclr vs. output power, test model 1 signal, 10.54 db par, 2170 mhz
adf4602 rev. a | page 13 of 36 ? 30 ?35 ?40 ?45 ?50 ?55 ?60 ?65 ?70 ?25 ?20 ?15 ?10 ?5 0 output power (dbm/3.84mhz) aclr (db) +5mhz ?5mhz +10mhz ?10mhz 07092-009 figure 11. txlbrf transmit aclr vs. output power, test model 1 signal, 10.54 db par, 881 mhz ref ?12.7dbm *att 0db * rbw 30khz * vbw 300khz * swt 100ms center 2.14ghz 2.55mhz/div span 25.5mhz 07092-010 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ? 100 ? 110 pos ?12.698dbm ch pwr acp low acp up alt1 low alt1 up ?8.08dbm ?57.05dbm ?57.09dbm ?70.92dbm ?71.41dbm figure 12. txhbrftransmit aclr, umts band i, 2140 mhz 2.6mhz/ span 26mhz 07092-110 ref ?20dbm *att 5db * rbw 30khz * vbw 300khz * swt 100ms center 1.96ghz ch pwr acp low acp up alt1 low alt1 up ?8.44dbm ?57.07dbm ?58.02dbm ?66.31dbm ?66.08dbm ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 figure 13. txhbrftransmit aclr, umts band ii, 1960 mhz ref ?10.9dbm *att 5db * rbw 30khz * vbw 300khz * swt 100ms marker 1 (t1) ?23.01dbm 880.877403846mhz center 881mhz 2.55mhz/div span 25.5mhz 07092-011 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ? 100 ? 110 pos ?10.895dbm ch pwr acp low acp up alt1 low alt1 up ?4.39dbm ?60.63dbm ?58.52dbm ?72.07dbm ?72.13dbm figure 14. txlbrf transmit aclr, umts band v, 881 mhz ? 51 ?53 ?55 ?57 ?59 ?61 ?63 ?65 2110 2120 2130 2140 2150 2160 2170 frequency (mhz) 5mhz aclr (db) 07092-012 0c 5mhz high 25c 5mhz high 85c 5mhz high 0c 5mhz low 25c 5mhz low 85c 5mhz low figure 15. transmit aclr vs. freque ncy and temperature (umts band i), transmit output power = ?8 dbm ? 51 ?53 ?55 ?57 ?59 ?61 ?63 ?65 1930 1940 1950 1960 1970 1980 1990 frequency (mhz) 5mhz aclr (db) 07092-013 0c 5mhz high 25c 5mhz high 85c 5mhz high 0c 5mhz low 25c 5mhz low 85c 5mhz low figure 16. transmit aclr vs. freque ncy and temperature (umts band ii), transmit output power = ?8 dbm
adf4602 rev. a | page 14 of 36 ? 54 ?56 ?58 ?60 ?62 ?64 ?66 865 870 875 880 885 890 895 frequency (mhz) 5mhz aclr (db) 07092-014 0c 5mhz high 25c 5mhz high 85c 5mhz high 0c 5mhz low 25c 5mhz low 85c 5mhz low figure 17. transmit aclr vs. freque ncy and temperature (umts band v), transmit output power = ?7 dbm 5 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 0.1 1 10 100 frequency (mhz) magnitude (dbm) 07092-015 figure 18. transmit baseband filter response ? 70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 1k 10k 100k 1m 10m 100m offset frequency (hz) phase noise (dbc/hz) 07092-016 figure 19. transmit synthesizer phase noise 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 ?34 ?32 ?30 ?28 ?26 ?24 ?22 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 output power (dbm/3.84mhz) current consumption (a) 07092-017 figure 20. current consumption vs. transmit output power; frequency = 2170 mhz, v dd = 3.3 v, test model 5 signal, receiver disabled ?120 ?100 ?80 ?60 ?40 ?20 0 0.1 1 10 magnitude (db) frequency (mhz) 07092-118 figure 21. receive wcdma baseband filter response 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1000 frequency (khz) magnitude (dbm) 07092-019 figure 22. receive gsm baseband filter response
adf4602 rev. a | page 15 of 36 16 14 12 10 8 6 4 2 0 20 30 40 50 60 70 80 90 receive gain setting (db) evm (%) 07092-020 mixstep = 10 lnastep = 6 gaincal = 8 figure 23. receive evm vs. gain; 2.84 mhz qpsk modulated input signal, wcdma receive baseband filter 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 20 30 40 50 60 70 80 90 100 receive gain setting (db) gain step (db) 07092-021 mixstep = 10 lnastep = 6 gaincal = 8 figure 24. receive gain step error vs. gain setting, 1 db steps, measurement was taken by injecting known signal level and measuring the gain through the device. the gain was then stepped through all settings in 1 db steps, and the gain step change measured in each case. 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 noise figure (db) rx gain (db) mixstep = 10 lnastep = 6 gaincal = 8 07092-122 figure 25. rxhb1rf, receiver noise figure vs. gain, umts band i, rx frequency = 1955 mhz 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 noise figure (db) gain (db) 07092-123 mixstep = 10 lnastep = 6 gaincal = 8 figure 26. rxhb2rf, receiver noise figure vs. gain, umts band ii, rx frequency = 1880 mhz 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 noise figure (db) gain (db) 07092-124 mixstep = 10 lnastep = 6 gaincal = 8 figure 27. rxlbrf, receiver noise figure vs. gain, umts band v, rx frequency = 836 mhz 20 18 16 14 12 10 8 6 4 2 0 1920 1930 1940 1950 1960 1970 1980 frequency (mhz) noise figure (db) 07092-023 25c 0c 85c gain = 80db figure 28. rxhbrf receive noise figure vs. frequency
adf4602 rev. a | page 16 of 36 16 14 12 10 8 6 4 2 0 1850 1860 1870 1880 1890 1900 1910 frequency (mhz) noise figure (db) 07092-024 25c 0c 85c gain = 80db figure 29. rxhb2rf receive noise figure vs. frequency 10 9 8 7 6 5 4 3 2 1 0 822 827 832 837 842 847 frequency (mhz) noise figure (db) 07092-025 25c 0c 85c gain = 80db figure 30. rxlbrf receive noise figure vs. frequency ?120 ?118 ?116 ?114 ?112 ?110 ?108 ?106 ?104 ?102 ? 100 1910 1920 1930 1940 1950 1960 1970 1980 1990 sensitivity (dbm) rx frequency (mhz) local area/ home bs ts25.104 limit 07092-126 figure 31. rxhb1rf receive sensitivity vs. frequency, umts band i (see the receive sensitivity section for more details) ?120 ?118 ?116 ?114 ?112 ?110 ?108 ?106 ?104 ?102 ? 100 1840 1850 1860 1870 1880 1890 1900 1910 1920 sensitivity (dbm) rx frequency (mhz) local area/ home bs ts25.104 limit 07092-127 figure 32. rxhb2rf receive sensitivity vs. frequency. umts band ii. ?120 ?118 ?116 ?114 ?112 ?110 ?108 ?106 ?104 ?102 ? 100 820 825 830 835 840 845 850 855 sensitivity (dbm) rx frequency (mhz) local area/ home bs ts25.104 limit 07092-128 figure 33. rxlbrf receive sensitivty vs. frequency. umts band v. ?14 ?16 ?18 ?12 ?10 ?8 ?6 ?4 ?2 0 2 0 10 20 30 40 50 60 70 80 90 100 110 receive gain setting (db) 10mhz + 19.8mhz ip3 (dbm) 07092-026 25c 0c 85c figure 34. rxhb1rf receive ip3, 10 mhz + 19.8 mhz vs. gain setting
adf4602 rev. a | page 17 of 36 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 0 10 20 30 40 50 60 70 80 90 100 110 receive gain setting (db) 85mhz + 190mhz ip3 (dbm) 07092-027 25c 0c 85c figure 35. rxhb1rf receive ip3, 85 mhz + 190 mhz vs. gain setting 50 55 60 65 70 75 80 85 90 95 100 105 110 0 10 20 30 40 50 60 70 80 90 100 110 receive gain setting (db) 190mhz ip2 (dbm) 07092-028 25c 0c 85c figure 36. rxhb1rf receive ip2, 190 mhz vs. gain setting ?10 ?12 ?14 ?8 ?6 ?4 ?2 0 2 4 6 8 0 10 20 30 40 50 60 70 80 90 100 110 receive gain setting (db) 80mhz + 40mhz ip3 (dbm) 07092-029 25c 0c 85c figure 37. rxhb2rf receive ip3, 80 mhz + 40 mhz vs. gain setting 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 110 receive gain setting (db) 80mhz ip2 (dbm) 07092-030 25c 0c 85c figure 38. rxhb2rf receive ip2, 80 mhz vs. gain setting 16 14 12 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 ?12 0 10 20 30 40 50 60 70 80 90 100 110 receive gain setting (db) 10mhz + 19.8mhz ip3 (dbm) 07092-031 25c 0c 85c figure 39. rxlbrf receive ip3, 10 mhz + 19.8 mhz vs. gain setting ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 14 16 0 10 20 30 40 50 60 70 80 90 100 110 receive gain setting (db) 45mhz + 22.5mhz ip3 (dbm) 07092-032 25c 0c 85c figure 40. rxlbrf receive ip3, 45 mhz + 22.5 mhz vs. gain setting
adf4602 rev. a | page 18 of 36 40 30 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 110 receive gain setting (db) 45mhz ip2 (dbm) 07092-033 25c 0c 85c figure 41. rxlbrf receive ip2, 45 mhz vs. gain setting
adf4602 rev. a | page 19 of 36 theory of operation transmitter description txbbi txbbib txbbq txbbqb gain control txpwr_set[11:0] ?90 degrees 2 2 txbs testq, swap_q testi, swap_i lpf lpf pa tx output lb only divider divider and quad gen integrated balun 07092-034 figure 42. transmitter block diagram the adf4602 contains a highly innovative low noise variable gain direct conversion transmitter architecture, that removes the need for external transmit saw filters. the direct conversion architecture significantly reduces the risk of transmit harmonics across all bands due to the simplified nature of the frequency plan. see figure 42 for a block diagram. i/q baseband the baseband interface for the i and q channels is a differential, dc-coupled input, supporting a wide range of input common- mode voltages (v cm ). the allowable input common-mode range is 1.05 v to 1.4 v. the maximum signal swing allowed is 550 mv peak differential. this corresponds to a 1.1 v peak-to- peak differential on either the i or q channel. figure 43 shows a graphical definition of peak differential voltage and v cm . the baseband input signals pass through a second order butterworth filter prior to the quadrature modulator. the cut- off frequency is 4 mhz. this gives some rejection of the dac images. the filter also helps to suppress any spurious signals that might be coupled to the baseband terminals on the pcb. for ease of pcb routing between the adf4602 and the transmit dac, the i and q differential inputs can be internally swapped. for user test purposes, the i and q inputs can also be internally shorted together and a dc offset applied. this produces a large carrier at the rf output, which is useful for signal path integrity testing. v cm i or q ib or qb peak v dif v olts time 07092-035 figure 43. transmit baseband input signals
adf4602 rev. a | page 20 of 36 i/q modulator the i/q modulator converts the transmit baseband input signals to rf. calibration techniques are used to maintain accurate iq balance and phase across frequency and environmental conditions, thus ensuring that 3gpp carrier leakage and evm and aclr requirements are met with good margin under all conditions. the on-chip calibrations are carried out during the transmit pll lock time specified and are self-contained, requiring no additional input from the user. the modulator has an 80 db gain control range, programmable in 1/32 of a decibel step. the 12-bit word txpwr_set[11:0] in register 28 controls the transmit output power. the setting is referenced to a full-scale (500 mv peak differential) sine wave signal applied to the transmit baseband inputs. to calculate the output power when a wcdma modulated signal with a certain peak-to-average ratio is applied, equation 1 should be used. output power (dbm/3.84 mhz) = txpwr (dbm) ? par(db) (1) where txpwr (dbm) is the txpwr_set[11:0] value converted to dbm, and par is the peak-to-average ratio of the wcdma signal. for example, if an output power of ?8 dbm is required for a wcdma signal with a peak-to-average ratio of 10 db txpwr (dbm) = ?8 dbm + 10 db = +2 dbm the current consumption of the modulator scales with output power. when the tx power is backed off from maximum, the transceiver benefits from lower power dissipation. vco output the tx vco output is fed to a tuned buffer stage and then to the quadrature generation circuitry. the tuned buffer ensures that minimum current and lo related noise is generated in the vco transport. this action is transparent to the user. the quadrature generator creates the highly accurate phased signals required to drive the modulator and also acts as a divide-by-2. in low band, an additional divide-by-2 is used in the vco transport path, which is bypassed in high band. this is done to minimize the vco tuning range required to cover all the bands. the phase accuracy of the signals is important in ensuring good modulation quality and accurate output power. an on-chip calibration ensures that the phased signals are exactly 90 out of phase. this calibration runs each time the frequency is changed or if the txpwr_set[11:0] word is written to. if the temperature of the device changes, this calibration should be updated. to run the calibration, the user should simply write to the txpwr_set[11:0] word for each five degree change in temperature, or update the value regularly (every few seconds) between wcdma frames or timeslots. this ensures that good evm and accurate output power are maintained as the temperature of the device changes. tx output baluns the baseband input, modulator, and all associated circuitry are fully differential to maintain high signal integrity and noise immunity. however, a differential output is not optimal for the user because most power amplifiers (pas) are singled-ended. this situation would normally require additional external matching components or a differential to single-ended saw filter structure. with the adf4602, the saw filter is not necessary, and the required low loss balun is fully integrated, converting the diffe- rential internal signals to a single-ended 50 output, thus allowing easy interfacing to the pa. the high band output is available at the txhbrf pin, and the low band output is available at the txlbrf pin. these are directly connected to a 50 load, if necessary, and do not require ac-coupling. dacs the adf4602 integrates two dacs that are designed to interface to an external pa to control reference or bias nodes within the pa. if this function is not required, the dacs are used for any general purpose or powered down if not required. dac1 is a 5-bit voltage output dac. the output range is from 2.3 v to 3.15 v (for v dd > 3.15 v). the dac1 output stage is supplied directly from vdd, with the capability to supply 10 ma of current to within 50 mv of v dd . for high accuracy, the dac reference is supplied from ldo5, which is internally trimmed to 25 mv accuracy. the dac1 output is set by the padac1[4:0] word. dac2 is a 6-bit voltage output dac with a range from 0 v to 2.8 v. ldo5 supplies both the reference voltage and full-scale output voltage for dac2. the output voltage is set by the padac2_ow[5:0] word. the dacgpo_owen bit must also be set high if control of dac2 is required. both dacs are powered down by writing the code, 0x0, to the respective control register. general purpose outputs four general-purpose outputs (gpos) are provided on the adf4602. these are used to control pa bias modes or, more commonly, the gpos are used to control external rf front-end switches in the transmit/receive path. the gpos are simple 3 v digital output drivers. gpo1 to gpo3 are capable of supplying a maximum current of 2 ma, whereas gpo4 can supply up to 10 ma. for operation of the gpos, bit dacgpo_owen must be set to 1. the gpos are then controlled via the gpo_ow[3:0] word. receiver description the adf4602 contains a fully integrated direct conversion receiver designed for multiband wcdma femtocell applications. high performance, low power consumption, and minimal external components are the key features of the design. figure 44 shows a block diagram of the receiver, which consists of three lna blocks for multiband operation, high linearity i/q mixers, advanced baseband channel filtering, and a dc offset compensation circuit.
adf4602 rev. a | page 21 of 36 gain control high band lna 1 high band lna 2 low band lna rxgain[6:0] vcmsel rxen[1:0] lna active filter changes mixer transconductance 0db to 18db 3 6db steps vga ?6db to +18db 24 1db steps 0db to 18db 3 6db steps 0db to 18db 3 6db steps 18db to 30db (wcdma) 27db to 39db (cdma) 2 6db steps rxhb2rf rxbbi rxbbib rxbbq rxbbqb rxhb1rf rxlbrf lpf lpf bpf bpf bpf dac dac rxbw_toggle adc adc lpf lpf lpf lpf programmable offset control 2 or 4 07092-036 figure 44. receiver block diagram lnas the adf4602 contains three tunable rf front ends suitable for all major 3gpp frequency bands. two are suitable for high band operation in the region 1700 mhz to 2170 mhz. one is suitable for operation from 824 mhz to 960 mhz. thus, the three integrated lnas offer the designer the opportunity to create multiband and regional specific variants with no additional components. lna power control and internal band switching is fully controlled by the serial interface. the adf4602 lnas are designed for 50 single-ended inputs, thus further simplifying the front-end design and providing easy matching with minimal components. typically, a two- component match is required: a series and shunt inductor. within the lna, the signal is converted to a differential path for signal processing in subsequent blocks within the receive signal chain. interstage rf filtering is fully integrated, ensuring that external out-of-band blockers are suitably attenuated prior to the mixer stages. the lna characteristic is designed to provide additional filtering at the transmitter frequency offset. the lnas are enabled by programming bits rxbs[1:0] in register 1. lna input rxhb1rf should be used for umts band i operation, and rxhb2rf should be used for umts band ii operation. mixers high linearity quadrature mixer circuits are used to convert the rf signal to baseband in-phase and quadrature components. although not shown in figure 44 , two mixer sections exist: one optimized for the high band lna outputs and one optimized for the low band. the high band and low band mixer outputs are combined and then driven directly into the first stage of the baseband low-pass filter, which also acts to reduce the level of the largest blocking signals, prior to baseband amplification. quadrature drive is provided to the mixers from the receiver synthesizer section by the vco transport system, which includes a programmable divider, so that the same vco is used for both high and low bands. excellent 90 quadrature phase and amplitude match are achieved by careful design and layout of the mixers and vco transport circuits. baseband section the adf4602 baseband section is a distributed gain and filter function designed to provide a maximum of 54 db gain with 60 db gain control range. through careful design, pass band ripple, group delay, signal loss, and power consumption are kept to a minimum. filter calibration is performed during the manufacturing process, resulting in a high degree of accuracy and ease of use. three baseband filters are available on the adf4602, as shown in table 5 . bits rxbw_toggle[2:0] are used to select the mode of operation. the seventh order wcdma filter with 1.92 mhz cutoff ensures that good attenuation of the adjacent channel should be used to meet blocking/adjacent channel selection specifications in femtocell applications. the gsm filter has a 100 khz cut-off and is intended for use as a monitoring receiver in a home base station. the fifth order wcdma filter provides less attenuation of the adjacent channel, so it should not be used in femtocell applications. the i and q channels can be internally swapped, thus allowing optimum pcb routing between radio and analog baseband. this is achieved using the swapi and swapq bits. table 5. receive baseband filter modes mode filter cutoff frequency f c seventh order wcdma 1.92 mhz fifth order wcdma 1.92 mhz gsm 100 khz
adf4602 rev. a | page 22 of 36 the receive baseband outputs have a programmable common mode voltage of 1.2 v or 1.4 v, selectable via the vcmsel bit in register 15. gain control gain control is distributed throughout the receive signal chain as shown in figure 46 . the rf front end contains 30 db of control range: 18 db in the lna and 12 db in the mixer transconductance stage. the two baseband active filter stages each provide 18 db of gain control range in 6 db steps. filter characteristics (ripple and group delay) are best conserved if the active filter stages have equal gain. this results in a total of 36 db gain control in 4 12 db steps for the filter stage. the variable gain amplifier (vga) implements 24 db of gain controllable in 1 db steps. the base gain of the mixer is 18 db, and the base gain of the vga is ?6 db. this gives a total of 102 db gain with 90 db of gain control range. the base gain of the mixer stage is 18 db in wcdma mode and 27 db in gsm mode. table 6. receive gain control in wcdma mode stage gain control control steps lna 0 db to +18 db 3 6 db steps mixer +18 db to +30 db (wcdma) +27 db to +39 db (gsm) 2 6 db steps filter 0 db to +36 db 3 12 db steps vga ?6 db to +18 db 24 1 db steps to simplify programming and to ensure optimum receiver performance and dynamic range, the user simply programs the total desired receive gain in db via the rx_gain[6:0] bits in register 11. the adf4602 then decodes the gain setting and automatically distributes the gain between the various blocks. to allow some flexibility, predefined user inputs control the gain threshold points at which the lna and mixer gain steps occur. bit settings mixstep[3:0] and lnastep[3:0] control the mixer and lna gain threshold steps, respectively. an excel spreadsheet detailing the receive gain decode system is available from analog devices, inc., on request. figure 45 shows an example gain distribution profile. 120 110 100 90 80 70 60 50 40 30 20 10 0 ?10 0 10 20 30 40 50 60 70 80 90 100 110 120 requested rx gain (db) block gain (db) 07092-037 rf gain baseband gain chip gain mixstep = 10 lnastep = 6 gaincal = 8 figure 45. gain distribution between rf and baseband blocks for default setting 50 45 40 35 30 25 20 15 10 5 0 ?5 ?10 0 10 20 30 40 50 60 70 80 90 100 110 120 requested rx gain (db) block gain (db) 07092-038 lna gain mixer gain filter gain vga gain mixstep = 10 lnastep = 6 gaincal = 8 figure 46. more detailed gain distribution profile in addition, a gain calibration setting in register 15 (gaincal[4:0]) is used to account for losses in the rf front end. the total gain in the adf4602 is given by receivegain = rxgain [6:0] ? gaincal [4:0] + x (2) where x = 8 in wcdma filter mode, and x = 17 in gsm filter mode. rxgain[6:0] is the receive gain programmed in register 11. gaincal[4:0] is the gain calibration setting in register 15, and is calculated using the following formula: gaincal [4:0] = 8 ? front_end_losses (3) where front_end_losses is the loss in the receive path due to duplexers/switches. this is useful for referencing the programmed gain to the antenna and accounting for any losses in the path. for example, if the total receive front-end loss is 2 db, the user should program gaincal[4:0] to 6 db. if the user then requestes 80 db of gain by programming rxgain[6:0] to 80 db, the adf4602 uses equation 4 to give receivegain = 80 ? 6 + 8 = 82 db (4) 82 db is the receive gain used internally by the adf4602.
adf4602 rev. a | page 23 of 36 dc offset compensation due to the very high proportion of the total system gain assigned to the analog baseband function, compensating for dc offsets is an inherent part of any direct conversion solution. dc offsets are characterized as falling into two categories: static or slow varying and time varying the adf4602 architecture has been designed to reduce the amount of time varying dc offsets. the device also includes a dc offset control system. the control system consists of adcs at the baseband output to digitize dc offsets: a digital signal processing block where the characteristics of the loop are programmed for customization of the loops transfer function, and trim dacs that are used to introduce the error term back into the signal path. the offset control transfer function can either be programmed to act as a servo loop that is automatically triggered by a gain change or as a high-pass filter (hpf) with an automatic fast settling mode that is also triggered by a gain change. parameters of the servo loop, high-pass filter, and fast settling mode are set by the initial adf4602 programming. in operation, the dc offset control system is fully automatic and does not require any external programming. recommended default programming conditions for the dc offset compensation loop are shown in the register description section. power management the adf4602 contains integrated power management requiring two external power supplies: 3.3 v vdd and 1.8 v vint. figure 47 shows a block diagram. vdd supplies the five integrated low drop-out regulators (ldos), vsup1 to vsup5, that are used to supply the vast majority of the internal circuitry. vsup6, vsup7, and vsup8 supply the receive pll, transmit pll, and reference block, respectively. these nodes require external connections to ensure good supply isolation and ensure a minimum level of interference between the pll/reference blocks and the rest of the transceiver. vsup6 and vsup7 should be connected to vsup3, whereas vsup8 should be connected to vsup2. each node, vsup1 to vsup8, should be externally decoupled to ground with a 0.1 f capacitor. y5v capacitors are not recommended for use here. x7r, x5r, c0g, or a similar type of capacitor should be used. c1 c3 c4 rx vco rx lnas tx vco 1.8v 2.8v 1.9v c6 c7 ref path ref op (ser int read) tx mod tx bb pwr det dacs rx baseband and mixers rx pll tx pll vsup8 vsup7 vsup6 vsup5 vsup4 vsup3 vsup2 vsup1 vbat vint c2 c5 analog bb or vsup2 digital 1.8v supply serial interface ldo 1 ldo 2 ldo 3 ldo 4 ldo 5 07092-039 figure 47. power management block vint supplies the serial interface enabling register data preservation with minimum current consumption during power-down. this should be supplied with 1.8 v externally. the five ldos are individually powered up/down via bits ldoen[4:0] in register 1. tabl e 7 summarizes the supply strategy. note that the reference path (vsup8) supply is supplied from an external source or the internal vsup2. the external supply option may be convenient so that the entire reference path can be shut down by collapsing a single supply. vsup8 can also be programmed to supply the voltage used for serial interface readback. see the serial port interface (spi) section for more information. table 7. power management strategy pin connection usage volts vint external serial interface control logic 1.8 v vdd external main device supply, dac1 3.3 v vsup1 internal ldo1 receive vco 2.6 v vsup2 internal ldo2 receive baseband and down-converter 2.8 v vsup3 internal ldo3 receive lnas 1.9 v vsup4 internal ldo4 transmit vco 2.6 v vsup5 internal ldo5 transmit baseband, modulator, dac2, and gpos 2.8 v vsup6 connect to vsup3 receive synthesizer 1.9 v vsup7 connect to vsup3 transmit synthesizer 1.9 v vsup8 vsup2 or external reference path, reference buffer outputs; optional: serial interface readback 2.8 v
adf4602 rev. a | page 24 of 36 frequency synthesis the adf4602 contains two fully integrated programmable frequency synthesizers for generation of transmit and receive local oscillator (lo) signals. the design uses a fractional-n architecture for low noise and fast lock-time. the fractional-n functionality is implemented with a third order - modulator. figure 48 shows a block diagram of the synthesizer architecture. pfd fref loop filter c p dividers digital decode rxfreq[15:0] 50khz step 2 lpf v co f vco : 3.4ghz to 4.4ghz range vco freq cal and amplitude control - ? phase frequency detector and charge pump 07092-040 figure 48. frequency synthesizer block diagram all necessary components are fully integrated for both transmit and receive synthesizers, including loop filters, vcos, and tank components. the vcos run at 2 the high band frequency and 4 the low band frequency. the dividers are external to the synthesizer loop. this minimizes vco leakage power at the desired frequency and tuning range requirements of the vco. the vcos use a multiband structure to cover the wide frequency range required. the design incorporates both frequency and amplitude calibration to ensure that the oscillator is always operating with its optimum performance. the calibrations occur during the 200 s pll lock time and are fully self contained, requiring no user inputs. the charge pump and loop filter are internally trimmed to remove variations associated with manufacture and frequency. this process is fully automated. to aid simplified programming, the adf4602 contains a frequency decode table for the synthesizers, meaning the programmer is not concerned with the internal operation of the counters and fractional-n system. frequency step sizes of 50 khz are possible with both transmit and receive synthesizers. the programming words rxfreq[15:0] and txfreq[15:0] set the frequency in 50 khz steps from 0 mhz to 3276.75 mhz. note that the synthesizers do not cover this full range. the frequency range for each synthesizer in high and low bands is given in the specifications section. when the high band is enabled, the programmed frequency is equal to the lo frequency. for low band operation, the programmed frequency should be set to 2 the desired lo frequency. the transmit and receive synthesizers are enabled by setting bit txsynthen and bit rxsynthen in register 1, respectively. reference path the adf4602 requires a 26 mhz reference frequency input. a vctcxo is used to provide this. the reference input is ac- coupled internally, so external ac coupling is not necessary. the 26 mhz reference is internally buffered and distributed to the respective blocks, such as the synthesizer pfd inputs. figure 49 shows a block diagram. the adf4602 provides two buffered outputs: a buffered version of the 26 mhz reference on pin refclk and a 19.2 mhz wcdma chip clock on pin chipclk. the 19.2 mhz chip clock is a multiple of the 3.84 mhz chip rate used in wcdma. thus, it can be used to clock adcs/dacs elsewhere in the system. the chip clock is generated by an integrated pll and contains no user settings. both outputs are slew rate limited and produce low swing digital outputs. the buffers contain their own 1.5 v regulator circuits to improve isolation and minimize unwanted supply noise. the 26 mhz and 19.2 mhz buffer outputs are enabled or disabled by programming bit refclken and bit chipclken (register 1). pll refin (26mhz) refclk chipclk vsup8 vsup8 vsup8 vsup8 reg reg 1.5v 1.5v chipclken refclken 26mhz clock distribution 07092-041 figure 49. reference path block diagram all reference sections are powered from vsup8, which can safely be removed from the chip in isolation, to enter a low current power-down mode. calibration data is not lost, but the reference frequency ceases to exist. as soon as vsup8 is re- applied, oscillation begins. this is visible at the buffer outputs, as long as they were previously enabled.
adf4602 rev. a | page 25 of 36 serial port interface (spi) the adf4602 contains internal registers that are used to configure the device. the three-wire serial port interface provides read and write access to the internal registers. for write, read requests, and read operations, 26-bit transfers are used. the msb of all words are transferred first. the read request format has the same address structure as the write format but does not contain a data field. padding is used to maintain the 26-bit word length. the readback format is the same as the word format during a write. again, padding is used to maintain the 26-bit word length. format table 9. spi chip select code figure 50 shows the format of the register write. this consists of a 5-bit address and 16-bit data words. the exception is register a1 = 00000, where the lower data byte is used as an 8-bit sub- address. in total, this creates 31 16-bit registers and 256 8-bit registers. the 31 16 bit registers are referred to in the text as register 31 for example, while the 256 8-bit sub registers are referred to as register 0.144. cs[2] cs[1] cs[0] device 0 0 1 adf4602 all other permutations reserved operation and timing sclk, sdata, and sen are used to transfer data into the adf4602 registers. data is clocked into the register, msb, first on the rising edge of each sclk. the data is transferred to the selected register address on the rising edge of sen. see figure 2 and figure 3 for timing information. op is a 2-bit code specifying the type of operation being performed (see table 8 for more information). the chip select code, cs, is a 3-bit field indicating which device on the bus is being programmed. for the adf4602, cs should be set to 001 (d2, d1, d0). read table 8. spi operation code figure 3 shows a read operation. first, a read request is written by the host to the adf4602. sen must remain high for at least three sclk periods between the read request operation and the following read operation. the host must release the sdata line during this period. the adf4602 takes control of sdata, and the read operation commences when the host device drives sen low. op[1] op[0] operation description 0 0 write normal register write. 0 1 set register bits corresponding to 1s in the data word are set. other bits are not modified. 1 0 clear register bits corresponding to 1s in the data word are cleared. other bits are not modified. 1 1 read register read request. the sdata output voltage during readback is set to 1.8 v or 2.8 v. bit sif_vsup8 (register 2) controls this. a 0 in this bit configures the device to use the 1.8 v vint supply, whereas a 1 configures the 2.8 v vsup8 supply. after power-up or after a soft reset, the adf4602 defaults to 2.8 v readback mode. bit position operation 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write register 1 to 31 w[25:0] write register 0 w[25:0] read request register 1 to 31 q[25:0] read request register 0 q[25:0] read register 1 to 31 q[25:0] read register 0 q[25:0] data d[15:0] random padding p[15:0] data d[7:0] subaddress a2[7:0] random padding p[7:0] subaddress a2[7:0] data d[7:0] subaddress a2[7:0] data d[15:0] address a1[4:0] address a1 = 00000 address a1[4:0] address a1[4:0] address a1 = 00000 address a1[4:0] op [1:0] op [1:0] op [1:0] op = 11 op = 11 op [1:0] cs [2:0] cs [2:0] cs [2:0] cs [2:0] cs [2:0] cs [2:0] 07092-042 figure 50. spi register write format
adf4602 rev. a | page 26 of 36 registers register map a1 1 2 w 0x2ffd rxsynth en reset_ soft sif_ vsup8 txsynth en chipclk en refclk en rxbs[1:0] txbs txen ldoen[4:0] rxen w 0x0002 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d3 d4 d2 d1 d0 default 1 r/w a1 10 11 12 13 14 15 w w w w w w 0x9858 rxfreq[15:0] 0x0000 rxgain[6:0] 0x0fa6 0x103e 0xee53 lnastep[3:0] nper0[3:0] nint0[3:0] mixstep[3:0] nper1[3:0] nint1[3:0] sdmen[3:0] nper2[3:0] nint2[3:0] rfskip[3:0] osadc2x[3:0] nint3[3:0] 0x0890 sdmosr gaincal[4:0] rxbw[2:0] swapi swapq vcmsel d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d3 d4 d2 d1 d0 default 1 r/w a1 21 22 26 28 31 31 w w w w w 0x001f vcm_sat_thres[5:0] cmmod test_q/swap_q test_i/swap_i gain_blanksel [1:0] 0x8000 padac1[4:0] padac2_ow[5:0] gpo_ow[3:0] dacgpo _owen 0x0000 txfreq[15:0] 0x0001 txpwr_set[11:0] cntrl_ mode 0x0000 nvmld r revid[7:0] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d3 d4 d2 d1 d0 default 1 r/w sub-address registers transmitter user registers receiver user registers general user registers a1 a2 0 144 0 151 0 153 0 155 0 165 0 170 w w w w w w 0x06 reserved[1:0] 0x6f 0x85 0x78 0x20 vsup2[7:0] reserved[7:0] reserved[7:0] reserved[7:0] 0xf0 en_mix[3:0] d7 d6 d5 d3 d4 d2 d1 d0 default 1 r/w 07092-043 notes 1 these are recommended default settings that should be programmed into the registers. 0x0021 figure 51. register map
adf4602 rev. a | page 27 of 36 register description table 10. general user registers register bit bit name description 13 rxen set this bit high to enable the receiver. a low here disables the receiver. 1, a1, write 12 refclken setting this bit high enab les the 26 mhz reference output buffer. 11 chipclken setting this bit high enab les the19.2 mhz chip clock output buffer. [10:6] ldoen the on-chip ldos are powered down individually. fo r normal operation all ldos should be enabled (bits[10 : 6] = [11111]) ldoen[10:6] 1 mode xxxx1 vsup1 2.6 v enable xxx1x vsup2 2.8 v enable xx1xx vsup3 1.8 v enable x1xxx vsup4 2.6 v enable 1xxxx vsup5 2.8 v enable 5 txen setting this bit high enables the transmitter. 4 txbs this bit controls which of th e transmit outputs is in use. 0 = low band (txlbrf), 1 = high band (txhbrf). 3 txsynthen setting this bit high enables the transmit synthesizer. [2:1] rxbs these bits control the receiver band select. rxbs[2:1] operation 00 reserved 01 low band enable (rxlbrf) 10 high band 1 enable (rxhb1rf) (default) 11 high band 2 enable (rxhb2rf) 0 rxsynthen setting this bit high enables the receive synthesizer 2, a1, write 1 sif_vsup8 the serial port readback (sdata) output voltage is chan ged from 1.8 v to 2.8 v with this bit. 0 = use 1.8 v vint supply, 1 = use 2.8 v vsup8 supply. after power-up or after a soft reset, the adf4602 defaults to 2.8 v readback mode. 0 reset_soft a rising edge on this bit starts a 50 s reset pulse for the full chip. this bit is self clearing. it is recommended that a soft reset be performed after power-up. 1 x = dont care.
adf4602 rev. a | page 28 of 36 table 11. receiver user registers register bit bit name description 10, a1, write [15:0] rxfreq these bits set the receive synthesizer frequency in 50 khz steps from 0 mhz to 3276.75 mhz. for the high bands this is equal to the channel frequency, and for the low bands it is 2 the channel frequency. for example: bit 15 to bit 0 (hex) rxhb1rf, rxhb2rf synthesizer frequency rxlbrf synthesizer frequency 0x9470 1900 mhz 950 mhz 0x9858 1950 mhz 975 mhz [6:0] rxgain these bits set the receiver gain in conjunctio n with the gaincal[4:0] setting in register 15. lsb = 1 db. 11, a1, write 0x00 = 0db, 0x7f = 127 db. gain = rxgain ? gaincal + x where x is 8 in wcdma mode and 17 in gsm mode. the mode is selected by the rxbw bits in register 15. with mixstep = 6 and lnastep = 10, the valid range for rxgain is from 12 db to 102 db. settings outside of these are clipped at 12 db and 102 db. see figure 45 for an example. [15:12] rfskip skip offset control state when no rf gain step occurred for state 3 to state 0. default = 0x0 = 0. 12, a1, write [11:8] sdmen - modulator enable for state 3 to state 0. default = 0xf = 15. [7:4] mixstep gain decode threshold for mixer gain reduction step. lsb = 4 db steps. default = 0xa = 10. [3:0] lnastep gain decode threshold for lna gain re duction step. lsb = 4 db steps. default = 0x6 = 6. [15:12] osadc2x offset measurement adc range for state 3 to state 0. default = 0x1 = 1. 13, a1, write [11:8] nper2 state duration for state 2. default = 0x0 = 0. [7:4] nper1 state duration for state 1. default = 0x3 = 3. [3:0] nper0 state duration for state 0. default = 0xe = 14. [15:12] nint3 integrator time constant for state 3. default = 0xe = 14. 14, a1, write [11:8] nint2 integrator time constant for state 2. default =0xe = 14. [7:4] nint1 integrator time constant for state 1. default = 0x5 = 5. [3:0] nint0 integrator time constant for state 0. default = 0x3 = 3. 11 vcmsel this sets the receive baseband output common-mode voltage. 0 = 1.2 v, 1 = 1.4 v. 15, a1, write 10 swapq setting this bit high swaps the differential q outputs, rxbbq and rxbbqb. 9 swapi setting this bit high swaps the differential i outputs, rxbbi and rxbbib. [8:6] rxbw this bit controls the receive baseband filter bandwidth. rxbw [8:6] filter mode 000 fifth order wcdma filter (not recommended for femtocells) 010 seventh order wcdma filter (recommended wcdma filter for femtocells) 111 gsm filter else reserved [5:1] gaincal these bits are used for calibration of front-end loss. ls b = 1 db, 0x00 = 0 db, 0x1f = 31 db. it is used in the calculation of the receive gain. see rxgain in register 11. if not used for calibration, this should be set to 8 in wcdma mode and 17 in gsm mode. 0 sdmosr offset loop - modulator over sampling ratio. 1 = 4, 0 = 2 (default)
adf4602 rev. a | page 29 of 36 table 12. transmitter user registers register bit bit name description [12:11] test_i/swap_i these bits allow various options on the i inputs as detailed in the following table: 21, a1, write bits function 00 normal operation 01 swap i differential inputs for ease of pcb routing to dac 10 zero input on i inputs 11 dc offset applied to i inputs; creates large carrier at rf [10:9] test_q/swap_q these bits al low various options on the q inputs as detailed in the table below: bits function 00 normal operation 01 swap q differential inputs for ease of pcb routing to dac 10 zero input on q inputs 11 dc offset applied to q inputs: creates large carrier at rf [8:7] gain_blanksel during a transmit gain change, some spectral spla tter may occur at the output of the transmitter. these bits allow the input baseband signal at the input to the low-pass filter to be blanked for a short period, to reduce the spectral splatter observed during the gain change. gain_blanksel[8:7] operation 00 default setting; no blanking 01 230 ns blanking 10 540 ns blanking 11 850 ns blanking 6 cmmod this bit adjusts the internal modulator common-mode setting. it should be set to 0. setting this bit to 1 results in reduced power consumpt ion but degrades transmit linearity. [5:0] vcm_sat_thres this bit should be set to 0x1f for normal operation. 15: dacgpo_owen setting this bit high allows the user to have manual control over dac2 and gpo1 to gpo4. 22, a1, write [14:11] gpo_ow these bits allow manual control of gpo 1 to gpo 4. bit dacgpo_owen must be set to 1 to allow this mode of operation. each bit controls one of the gpos as per the following table. this allows all possible permutations of gpo output combinations. gpo_ow[14 :11] 1 mode xxx1 gpo1 high xx1x gpo2 high x1xx gpo3 high 1xxx gpo4 high [10:5] padac2_ow these bits allow manual control of dac2. bit dacgpo_ owen must be set to 1 to allow this mode of operation. [4:0] padac1 these bits control dac1. 26, a1, write [15:0] txfreq these bits set the transmitter synthesizer frequency in 50 khz steps from 0 mhz to 3276.75 mhz. for the high bands, this is equal to the channe l frequency, and for the low bands it is 2 the channel frequency. for example: bit 15 to bit 0 (hex) hb synthesizer frequency lb synthesizer frequency 0xa730 2140 mhz 1070 mhz 0xa988 2170 mhz 1085 mhz
adf4602 rev. a | page 30 of 36 register bit bit name description 28, a1 write [15:4] txpwr_set requested transmit power at antenna. lsb = 1/32 dbm, 0x000 = ?80 dbm, 0xfff = 47.96875 dbm. the output power is referenced to a full scale sine wave applied to the tr ansmit baseband inputs. for wcdma modulated signals, the output power measured in a 3.84 mhz bandwidth is reduced by the peak to average ratio of the signal. see the i/q modulator section for more details. the valid range of transmit output power setting is ?80 db m to +10 dbm. output clipping may occur sooner, depending on the par of the applied signal. the txpwr_set register should be updated periodica lly, or with every 5c change in temperature to ensure accurate output power. see the vco output section for more details. 0 set this bit to 1 to control the output power from the txpwr_set bits. 31, a1 write 4 nvmld setting this bit to 1 triggers a manual load of the nonvolatile memory contents. see the software initialization procedure section for more details. 31, a1 read [7:0] revid chip revision id. revision represented in hex value. a readback of 0x21 represents rev 2.1. 1 x = dont care. table 13. sub-address registers register bit bit name description 0.144, a2 write [2:1] reserved[1:0] these bits should be set to 11 for normal operation. 0.151, a2 write [7:0] vsup2[7:0] these bits control the vsup2 regulator voltage and should be set to 0x6f for normal operation. during the initialization sequence , the vsup2 voltage is temporarily set to 3.1 v. see the software initialization procedure section for more details. 0.153, a2 write [7:0] reserved[7:0] these bits should be set to 0x85 for normal operation. 0.155, a2 write [7:0] reserved[7:0] these bits should be set to 0x78 for normal operation. 0.165, a2 write [7:0] reserved[7:0] these bits should be set to 0x20 for normal operation. 0.170, a2 write [7:4] en_mix[3:0] these bits enable the i, ib, q, and qb channe ls of the modulator separately. set these bits to all 1s to enable the modulator for normal operation.
adf4602 rev. a | page 31 of 36 software initialization procedure initialization sequence table 14 shows the initialization sequence that should be used after power-up. note that the 26 mhz reference clock must be applied to the refin pin before programming begins. the default settings are described in the comments section, and some settings, such as output frequency, gain, and gpo settings, may vary from those required in the end application of the user. the user can substitute his own settings in these instances. table 14. initialization sequence step register 1 data comment 1 02 0x0003 performs a soft reset of the adf4602. the reset takes 50 s , and no registers should be written to during this period. after 50 s, programming can continue as normal. this bit is self clearing. if using 1.8 v logic levels, this register sh ould be programmed to 0x0001 instead of 0x0003. 2 0.151 0xe0 set vsup2 to 3.1 v. see the nonvolatile memory (nvm) initialization section for more details. 3 31 0x0010 transfers non-volatile memory (nvm) contents to registers. wait 200 s before next programming step. 4 31 0x0000 negate bit set in last programming step. 5 0.151 0x6f set vsup2 back to 2.8 v. 6 01 0x2fdd enables receiver and disables trans mit output. selects txhbrf pin as the transmit output and rxhb1rf as the receive input. enables all on-chip regulators. 19.2 mhz output clock is enabled, 26 mhz output clock is disabled. if it is desired to disable the 19.2 mhz output clock, this register is programmed to 0x27dd. 7 12 0x0fa6 default settings for mixer and lna gain reduction steps. 8 13 0x103e default settings. 9 14 0xee53 default settings. 10 15 0x0890 sets received gain calibration, wcdma filter mode, and output common-mode voltage to 1.4 v. 11 21 0x001f default settings. 12 22 0x8000 enables dac and gpo manual control. 13 0.144 0x06 default settings. 14 0.155 0x78 default settings. 15 0.153 0x85 default settings. 16 0.165 0x20 default settings. 17 0.170 0xf0 default settings. 18 11 0x0050 receiver gain set to 80 db. 19 10 0x9858 receiver synthesizer frequency set to 1950 mhz. the pll takes 200 s to lock. registers should not be written to during this period. 20 26 0xa730 transmit synthesizer frequency set to 2140 mhz. the pll takes 200 s to lock. registers should not be written to during this period. 21 01 0x2ffd enables transmit output. 22 28 0xa001 enables control of the output power and sets the txpwr_ set field to 0 dbm. control of output power is via the txpwr_set bits. 1 register numbers 0.xxx are 8-bit regist ers as described in the spi interface section of the adf4602-x data sheet.
adf4602 rev. a | page 32 of 36 nonvolatile memory (nvm) initialization the adf4602 has on-chip non-volatile memory (nvm) that contains chip factory calibration coefficients. a soft reset of the device transfers the contents of nvm to internal registers; however, this has been found to be unreliable if performed at temperatures below 0c. the software work-around outlined in step 2 to step 5 of tabl e 14 ensures that the nvm data is transferred reliably under all operating conditions. it involves setting the vsup2 on-chip regulator to 3.1 v, manually transferring the data by setting the nvmld bit in register 31, and then resetting the vsup2 regulator to 2.8 v. device programming can then continue as normal. programming transmit and receive frequencies after initialization, the transmit/receive synthesizer frequencies may need to be changed. to change the transmit frequency, write the new frequency word to register 26. when a new transmit frequency is programmed, the transmit output power is auto- matically turned off to prevent any unwanted transmissions as the pll locks. the user should wait 200 s (time taken for pll to lock), and then set the output power to the desired value by writing to register 28. if the user disables the transmit synthesizer, the transmit output power must be turned off before reenabling the transmit synthesizer. this is achieved by two means: setting bit d5 in register 1 or setting the output power in register 28 to a minimum. after reenabling the synthesizer, and then locking the synthesizer to a frequency by programming the frequency word in register 26, the user can reenable the output power. to change the receive frequency, simply program the new frequency in register 10, and wait 200 s before using the device as a transceiver. the receive gain is set at any time (apart from during the 200 s pll locking transient).
adf4602 rev. a | page 33 of 36 applications information interfacing the adf4602 to the ad9963 ad9963 adc inputs the ad9963 rx path analog inputs have a nominal differential impedance of 4 k. the nominal dc bias level of the inputs is 1.4 v. an internal differential voltage reference creates positive and negative reference voltages that define the full-scale input voltage of the adcs. this full-scale input voltage range can be adjusted by means of the rx_fsadj[4:0] parameter in configuration register 0x7d. rx_fsadj should be set to 0x1f for default operation with the adf4602. this sets the peak-to-peak input voltage range to the midrange value of 1.54 v. interfacing to the ad9963 rx baseband inputs the adf4602 baseband outputs have a nominal output common-mode voltage that can be set to 1.4 v. the adf4602 can be dc-coupled to the ad9963. it is recommended that a first-order low-pass filter be placed between the two devices to reject unwanted high frequency signals that may alias into the desired baseband signal. 100 ? 100 ? 68pf 68pf adc ad9963 adf4602 rxip rxin rxbbi rxbbib 08801-118 figure 52. adf4602 to ad9963 receive interface circuit in this configuration, the adf4602 is setting the common- mode input voltage of the ad9963 adcs to 1.4 v. the input common-mode buffer of the ad9963 should be disabled (set register 0x7e, bit 1 = 1) to avoid contention with the adf4602 output driver. ad9963 dac outputs the ad9963 dac contains a current source array capable of providing a nominal full-scale current (i outfs ) of 2 ma. dac full-scale output current is regulated by the reference control amplifier and is determined by the product of a reference current, a programmable reference resistor, r ref , an internal programmable resistor, r set , and a pair of programmable gain scaling parameters. reference voltage there is a single reference voltage that is used by both the i and q channel dacs. the ad9963 refio reference voltage is generated by an internal 100 a current source terminated into a programmable resistor, r ref . the resistance can be varied by adjusting the refio_adj[5:0] bits in register 0x6e, if necessary. for default operation, refio_adj should be set to zero. this nominal r ref resistance is 10 k resulting in a 1.0 v reference voltage. the ad9963 refio pin should be decoupled to agnd with a 0.1 f capacitor. current scaling resistor, rset each transmit dac has a resistor that is used to adjust the full- scale current. the nominal resistance is 16 k, which results in a full-scale current of 2 ma (when v refio equals 1.0 v). the 6-bit programmable values, irset[5:0] and qrset[5:0] (register 0x6a and register 0x6d) should be set to zero for this default operation. gain scaling parameters each transmit dac has coarse and fine gain control parameters for scaling the full-scale output currents. these adjustments change only the full-scale current of the dac and have no impact on the refio voltage. the coarse scale adjust (gain1) allows the nominal output current to be changed by 6 db in approximately 0.25 db steps. the adjustment range of the fine scale adjust (gain2) is about 2.5%. these settings can be found in the 0x68, 0x69, 0x6b, and 0x6c registers and in bits five to zero. gain1 should be set to 0x01 and gain2 should be set to zero for default operation. receive sensitivity figure 31 shows the adf4602 receive sensitivity vs. frequency for umts band i using the rxhb1rf input port. the sensitivity degradation due to the 63 rd and 64 th harmonics of the 30.72 mhz adc sampling frequency can be seen near 1935 mhz and 1966 mhz. the sensitivity degradation caused by these harmonics was minimized by placing 100 series resistors and 68 pf filtering capacitors at the adc inputs (see figure 52 ). note the sensitivity degradation due to the 76 th frequency harmonic of the 26 mhz reference at 1976 mhz. the degra- ation in sensitivity is less than 3 db for these harmonics. overall, the solution exceeds the 3gpp sensitivity specifications by 7 db across the frequency range. in addition, note that the 100 f capacitors to ground at the ad9963 dac outputs will minimize sensitivity degradation due to dac clock harmonics, particularly in umts sniff mode.
adf4602 rev. a | page 34 of 36 interfacing to the ad 9963 tx baseband outputs the adf4602 transmit baseband inputs accept a 1.2 v common- mode input signal with 1 v p-p differential swing. the configu- ration in figure 53 is used to provide this from the ad9963 txdacs. the ad9963 can be dc coupled to the adf4602 as shown in figure 53 . when configured for a 2 ma full-scale current, the output swing of the circuit is 1 v p-pd. centered at 1.2 v. the ad9963 txmcl pin is biased at 0.5 v to increase the headroom of the dac outputs. the ad9963 txvdd and clk33v supplies must be supplied with 3.3 v to support this output compliance range from the dacs. the optional 100 k resistors connected between the auxio pins and the txin (and txqn) pins allow a dc offset to be provided to null out carrier leakage at the adf4602 outputs. 07092-129 226? 249? 0.1uf 249? 249? 100k ? 226? 249 ? 249 ? 249? 100k ? txin txip txcml auxio2 txqn auxio3 txqp txbbqb txbbq txbbi txbbib ad9963 adf4602 100pf 100pf 100pf 100pf figure 53. ad9963 to adf4602 tx interface circuitry .
adf4602 rev. a | page 35 of 36 outline dimensions 1 40 10 11 31 30 21 20 4.25 4.10 sq 3.95 top view 6.00 bsc sq pin 1 indicator 5.75 bsc sq 12 max 0.30 0.23 0.18 0.20 ref seating plane 1.00 0.85 0.80 0.05 max 0.02 nom coplanarity 0.08 0.80 max 0.65 typ 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bot tom view) compliant to jedec standards mo-220-vjjd-2 072108-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 54. 40-lead lead frame chip scale package [lfcsp_vq] 6 mm 6 mm body, very thin quad (cp-40-1) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adf4602bcpz 0c to +85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 ADF4602BCPZ-RL 0c to +85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 ev-adf4602eb3ztst baseband adapter board eval-adf4602eb3z umts band i femtocell base station evaluation board. includes umts mode. eval-adf4602eb5z umts band ii/band v femtocell base station evaluation board. includes umts mode. 1 z = rohs compliant part.
adf4602 rev. a | page 36 of 36 notes ?2009C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07092-0-2/11(a)

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